Loop Termination Buffer
A SystemVerilog loop-termination predictor integrated into the BlackParrot RISC-V processor.
I implemented a SystemVerilog branch predictor for the pattern \((1^N0)^M\), where \(N\) is the inner-loop size and \(M\) is the outer-loop size, and integrated it into the BlackParrot RISC-V processor. The implementation is based on Loop Termination Prediction by Timothy Sherwood and Brad Calder.